Publications

Books (edited)

  1. E. Macii, V. Paliouras, O. Koufopavlou, editors, Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation 14th International Workshop, PATMOS 2004, Lecture Notes in Computer Science (LNCS 3254), Spinger Verlag, 2004. (ISBN: 3-540-23095-5)
  2. V. Paliouras, J. Vounckx and D. Veerkest, editors, Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation 15th International Workshop, PATMOS 2005, Lecture Notes in Computer Science (LNCS 3728), Spinger Verlag, 2005. (ISBN: 3-540-29013-3)
  3. V. Paliouras, Th. Stouraitis, A. Ioinovici, editors, Advanced Signal Processing, Circuits, and System Design Techniques for Communications, IEEE, 2006. (ISBN: 1-4244-0460-6)
  4. E. Macii, V. Paliouras, T. Stouraitis, technical program co-chairs and general chair, Proceedings of 2010 17th IEEE International Conference on Electronics, Circuits and Systems, IEEE, (ISBN: 978-1-4244-8157-6)

Textbook

  1. ΝΙΚΟΛΑΟΣ ΑΒΟΥΡΗΣ, ΜΙΧΑΗΛ ΚΟΥΚΙΑΣ, ΒΑΣΙΛΗΣ ΠΑΛΙΟΥΡΑΣ, ΚΥΡΙΑΚΟΣ ΣΓΑΡΜΠΑΣ, PYTHON – ΕΙΣΑΓΩΓΗ ΣΤΟΥΣ ΥΠΟΛΟΓΙΣΤΕΣ – 4η αναθεωρημένη και επαυξημένη έκδοση, in greek, Πανεπιστημιακές Εκδόσεις Κρήτης, 2018

Articles in journals

  1. Vasilis Sakellariou, Vassilis Paliouras, Ioannis Kouretas, Hani Saleh, Thanos Stouraitis, “A multiplier-free RNS-based CNN accelerator exploiting bit-level sparsity,” in IEEE Transactions on Emerging Topics in Computing, Special Section on Computer Arithmetic, 2023, doi:10.1109/TETC.2023.3301590.
  2. K. Papachatzopoulos and V. Paliouras, “Noise-Shaping Binary-to-Stochastic Converters for Reduced-Length Bit-Streams,” in IEEE Transactions on Emerging Topics in Computing, 2023, doi: 10.1109/TETC.2023.3299516.
  3. K. Papachatzopoulos and V. Paliouras, “Path-Based Delay Variation Models for Parallel-Prefix Adders,” IEEE Transactions on Emerging Topics in Computing, February 2023
  4. D. Vordonis and V. Paliouras, “Hardware Implementation and Performance Analysis of Improved Sphere Decoder in spatially correlated Massive MIMO channels,” IEEE Open Journal of the Communications Society, vol. 2, pp. 2680-2694, December 2021 (also published as TechRxiv preprint)
  5. G. Dimitrakopoulos, K. Papachatzopoulos, V. Paliouras, “Sum-propagate adders,” IEEE Transactions on Emerging Topics in Computing, vol. 9, no. 3, pp. 1479-1488, 1 July-Sept. 2021, Special section on ARITH 2021
  6. A. Mahdi, N. Kanistras, and V. Paliouras, “A Lightweight – Ultrafast Encoder for the IEEE 802.11n/ac/ax QC-LDPC Codes,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 1, pp. 51-64, Jan. 2021, doi: 10.1109/TVLSI.2020.3034046.
  7. I. Kouretas and V. Paliouras, “Hardware Implementation of a Softmax-Like Function for Deep Learning,” Special Issue on MOCAST 2019, (Extended version of the IEEE MOCAST 2019 paper), MDPI Technologies, 8(3), August 2020.
  8. M. G. Arnold, V. Paliouras and I. V. Kouretas, “Implementing the Residue Logarithmic Number System Using Interpolation and Cotransformation,” IEEE Transactions on Computers, vol. 69, no. 12, pp. 1719-1732, 1 Dec. 2020, doi: 10.1109/TC.2019.2930514
  9. K. Papachatzopoulos and V. Paliouras, “Static Delay Variation Models for Ripple-Carry and Borrow-Save Adders,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 7, pp. 2546-2559, July 2019, doi: 10.1109/TCSI.2019.2900151
  10. K. Papachatzopoulos and V. Paliouras, “Low-Power Addition with Borrow-Save Adders under Threshold Voltage Variability,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 65, no. 5, pp. 1 – 5, May 2018, (Journal special issue on IEEE ISCAS 2018).
  11. P. Sakellariou and V. Paliouras, “Reconfigurable RO-Path Delay Sensor,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 65, no. 12, pp. 2027-2031, December 2018, doi: 10.1109/TCSII.2018.2798503.
  12. I. Tsatsaragkos and V. Paliouras, “A reconfigurable LDPC decoder optimized for 802.11n/ac applications,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 1, pp. 182 – 195, January 2018.
  13. P. Sakellariou and V. Paliouras, “Application-specific low-power multipliers based on selective activation,” IEEE Transactions on Computers, vol. 65, no. 10, pp. 2973 – 2985, October 1, 2016.
  14. A. Mahdi and V. Paliouras, “On the Encoding Complexity of Quasi-Cyclic LDPC Codes,” IEEE Transactions on Signal Processing, vol. 63, no. 22, pp. 6096 – 6108, November 15, 2015.
  15. I. Tsatsaragkos and V. Paliouras, “Approximate Algorithms for Identifying Minima on Min-Sum LDPC Decoders and Their Hardware Implementation,” IEEE Transactions on Circuits and Systems II (TCAS-II), vol. 62, no. 8, pp. 766 – 770, August 2015.
  16. A. Mahdi and V. Paliouras, “A Low Complexity – High Throughput QC-LDPC Encoder,” IEEE Transactions on Signal Processing, vol. 62, no. 10, pp. 2696 – 2708, May 15, 2014.
  17. I. Kouretas, Ch. Basetas, and V. Paliouras, “Low-power Logarithmic Number System Addition/Subtraction and their Impact on Digital Filters”, IEEE Transactions on Computers, 62(11), November 2013, pp. 2196 – 2209.
  18. Ν. Kanistras and V. Paliouras, “Impact of approximation error on the decisions of LDPC decoding,” Journal of Signal Processing Systems, 64, pp. 41 – 59, Springer, July 2011.
  19. I. Kouretas and V. Paliouras, “A Low-Complexity High-Radix RNS Multiplier,” IEEE Transactions on Circuits and Systems, Part I, 2009. Printed: vol. 56, issue 11, pp. 2449 – 2462, November 2009.
  20. T. Giannopoulos andV. Paliouras, “A Low-Complexity PTS-based PAPR Reduction Technique for OFDM Signals without Transmission of Side Information,” Journal of Signal Processing Systems, 2008 – (special issue on sips 2006). printed edition: Issue 56:2-3, Springer, September 2009.
  21. G. Dimitrakopoulos and V. Paliouras, “A novel architecture and a systematic graph-based methodology for modulo multiplication”, IEEE Transactions on Circuits and Systems – Part I, Vol. 51, No. 2, pp. 354 – 370, February 2004.
  22. Τ. Stouraitis and V. Paliouras, “Considering the Alternatives in Low-Power Design”, IEEE Circuits and Devices Magazine, Vol. 17, No. 4, pp. 23–29, July 2001.
  23. V. Paliouras, K. Karagianni and T. Stouraitis, “A Low-complexity Combinatorial RNS Multiplier”, IEEE Transactions on Circuits and Systems – Part II, Vol. 48, No. 7, pp. 675–683, July 2001.
  24. K. Karagianni, V. Paliouras, G. Diamantakos and T. Stouraitis, “Operation-saving VLSI Architectures for 3-D Geometrical Transformations”, ΙΕΕΕ Transactions on Computers, Vol. 50, No. 6, pp. 609–622, June 2001.
  25. V. Paliouras and T. Stouraitis, “Novel High-Radix Residue Number System Architectures”, ΙΕΕΕ Transactions on Circuits and Systems – Part II, Vol. 47, No. 10, pp. 1059–1073, October 2000.
  26. V. Paliouras, K. Karagianni and T. Stouraitis, “A Floating-point Processor for Fast and Accurate Sine/Cosine Evaluation”, ΙΕΕΕ Transactions on Circuits and Systems – Part II, Vol. 47, No 5, pp. 441–451, May 2000.
  27. V. Paliouras and T. Stouraitis, “Multi-function architectures for RNS processors”, IEEE Transactions on Circuits and Systems – Part II, Vol. 46, No. 8, pp. 1041–1054, August 1999. This article received the IEEE Circuits and Systems Society 2000 Guillemin-Cauer Award.
  28. V. Paliouras, K. E. Karagianni and T. Stouraitis, “Error bounds for floating-point polynomial interpolators”, IEE Electronics Letters, Vol. 35, No. 3, pp. 195–197, 4 February 1999.
  29. D. Soudris, V. Paliouras, T. Stouraitis and G. Thanailakis, “Design methodology for the implementation of multidimensional circular convolution”, IEE Proceedings-Circuits, Devices, and Systems, 144(6): pp. 323–328, December 1997.
  30. D. J. Soudris, V. Paliouras, T. Stouraitis and C. E. Goutis, “A VLSI design methodology for RNS full adder-based inner product architectures”, IEEE Transactions on Circuits and Systems – Part II, Vol. 44, No. 4, pp. 315–318, April 1997.

Book chapters

  1. V. Paliouras, “Logarithmic Number System and its Application in FIR Filter Design,” book chapter, in Embedded Systems Design with Special Arithmetic and Number Systems, ISBN 978-3-319-49742-62017, Springer, 2017.
  2. V. Paliouras and T. Stouraitis, “Logarithmic Number System,” Book chapter, in Arithmetic Circuits for DSP applications, ISBN-10: 1119206774, ISBN-13: 9781119206774 Publisher: Wiley-IEEE Press, 2017.
  3. V. Paliouras και T. Stouraitis, “Computer Arithmetic Techniques for Low-power Systems”, στο Designing CMOS Circuits for Low Power, D. Soudris, C. Piguet, και C. Goutis, επιμελητές, σελ. 97 – 116, ESDLPD Book Series, Kluwer Academic Publishers, 2002.
  4. D. J. Soudris, E. D. Kyriakis-Bitzaros, V. Paliouras, M. K. Birbas, T. Stouraitis και C. E. Goutis, “On the design of two-level pipelined processor arrays”, στο Application-Driven Architecture Synthesis, F. Catthoor και L. Svensson, επιμελητές, σελ. 95 – 118, Kluwer Academic Publishers, 1993.

Patents

  1. Ι. Tsatsaragkos and V. Paliouras, Reconfigurable Barrel Shifter and Rotator, US Patent No. 8713399, Issue date of patent: April 29th, 2014.
  2. I. Tsatsaragkos, A. Mahdi, N. Kanistras, V. Paliouras, LDPC Encoding and Decoding Techniques. US Patent No. 8739001, Issue date of patent: May 27th, 2014.
  3. I. Tsatsaragkos, N. Kanistras, and V. Paliouras, Method and apparatus for identifying selected values from among a set of values, Filed: October 2013. Ιssue date of patent: 6 Ιανoυαρίου 2015. US Patent No. 8930790, Application No: 14/027,081. Also published as WO2015036122A1 (19 Mar 2015). CN105556851A, EP3044882A1.
  4. A. Mahdi, N. Kanistras, V. Paliouras, Low Density Parity Check encoder and encoding method. US Patent Νο. 9,003,257B1. Date of Patent: Apr. 7, 2015. Also published as Encoding of low-density parity check for different low-density parity check (ldpc) codes sharing common hardware resources, WO2015039759 A1, (26 Mar 2015)

Articles in conference proceedings

  1. Emmanouil Kavvousanos, Vasilis Sakellariou, Vassilis Paliouras, Ioannis Kouretas and Thanos Stouraitis, “Improving Residue-Level Sparsity in RNS-based Neural Network Hardware Accelerators via Regularization” accepted for presentation at ARITH 2023, Portland, Oregon.
  2. I. Kouretas, V. Paliouras, T. Stouraitis, “Modified Logarithmic Multiplication Approximation for Machine Learning,” IEEE AICAS 2023, Hangzhou, China
  3. Dimitris Kompostiotis, Dimitris Vordonis, Vassilis Paliouras, and G. A. Alexandropoulos, “Secrecy Rate Maximization in RIS-Enabled OFDM Wireless Communications: The Circuit-Based Reflection Model Case,” accepted for presentation at IEEE ICC Workshop on Holographic MIMO Communications, Roma, Italy, 2023
  4. Dimitris Kompostiotis, Dimitris Vordonis, and Vassilis Paliouras, “Received Power Maximization with Practical Phase-dependent Amplitude Response in RIS-Aided OFDM Wireless Communications”, IEEE ICASSP 2023
  5. A. El-Kady, AP. Fournaris, E. Haleplidis, V. Paliouras, “High-Level Synthesis design approach for Number-Theoretic Multiplier,” 2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC)
  6. D. Vordonis, D. Kompostiotis, and V. Paliouras, “Reconfigurable Intelligent Surface-Aided OFDM Wireless Communications: Hardware Aspects of Reflection Optimization Methods,” MOCAST 2022
  7. E. Kavvousanos and V. Paliouras, “A Low-Latency Syndrome-based Deep Learning Decoder Architecture and its FPGA Implementation,” MOCAST 2022.
  8. T. Spanos and V. Paliouras, “Hardware aspects of iterative receivers for V2X applications,” MOCAST 2022.
  9. Kleanthis Papachatzopoulos and Vassilis Paliouras, “Sensitivity to Threshold Voltage Variations of Exact and Incomplete Prefix Addition Trees”, IEEE ISCAS 2022.
  10. Vasilis Sakellariou, Vassilis Paliouras, Ioannis Kouretas, Hani Saleh, Thanos Stouraitis, “Α High-performance RNS LSTM block”, IEEE ISCAS 2022.
  11. Alexander El-Kady, Apostolos P. Fournaris, Thanasis Tsakoulis, Evangelos Haleplidis, Vassilis Paliouras, “High-Level Synthesis design approach for Number-Theoretic Transform Implementations,” VLSISOC 2021.
  12. V. Sakellariou, I. Kouretas, V. Paliouras, T. Stouraitis, “On Reducing the Number of Multiplications in RNS-Based CNN Accelerators,” ICECS 2021.
  13. D. Chytas and V. Paliouras, “A 5G-code based iterative Non-Binary LDPC decoder,” ICECS 2021.
  14. E. Kavvousanos and V. Paliouras, “Optimizing Deep Learning Decoders for FPGA Implementation,” FPL 2021.
  15. I. Kouretas and V. Paliouras, “Hardware aspects of parallel neural network implementation,” 10th International Conference on Modern Circuits and Systems Technologies (MOCAST), 2021.
  16. Chr. Andriakopoulos, K. Papachatzopoulos, V. Paliouras, “A Novel Stochastic Polar Architecture for All-Digital Transmission,” 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021.
  17. I. Kouretas and V. Paliouras, “Simplified Hardware Implementation of Memoryless Dot Product for Neural Network Inference,” 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021.
  18. V. Sakellariou and V. Paliouras, “An FPGA Accelerator for Spiking Neural Network Simulation and Training,” ISCAS 2021.
  19. E. Kavoussanos and V. Paliouras, “An Iterative Approach to Syndrome-based Deep Learning Decoding,” 2020 IEEE Globecom Workshops (GC Wkshps): IEEE GLOBECOM 2020 Open Workshop on Machine Learning in Communications.
  20. D. Chytas and V. Paliouras, “Approximate Sorting Check Node Processing in Non-Binary LDPC Decoders,” IEEE ICECS 2020.
  21. K. Papachatzopoulos and V. Paliouras, “Maximum Delay Models for Parallel-Prefix Adders under Threshold Voltage Variations,” ΙΕΕΕ Symposium on Computer Arithmetic (ARITH) 2020.
  22. K. Papachatzopoulos, Ch. Andriakopoulos, and V. Paliouras, “Novel Noise-Shaping Stochastic-Computing Converters for Digital Filtering”, IEEE ISCAS 2020, Seville, Spain
  23. E. Kavvousanos and V. Paliouras, “Hardware Implementation Aspects of a Syndrome-based Neural Network Decoder for BCH Codes”, 2019 IEEE NorCAS.
  24. D. Vordonis and V. Paliouras, “Sphere Decoder for Massive MIMO Systems”, 2019 IEEE NorCAS.
  25. K. Karagianni and V. Paliouras, “Versatile Hardware Generation of alpha-Stable Noise for PLC Channel Emulation”, IEEE ICECS 2019.
  26. M. Arnold, I. Kouretas, V. Paliouras and A. Morgan, “One-Hot Residue Logarithmic Number Systems”, PATMOS 2019.
  27. I. Kouretas and V. Paliouras, “Radix-3 low-complexity modulo-M multipliers”, PATMOS 2019.
  28. Mark G. Arnold, Ioannis Kouretas, Vassilis Paliouras, John R. Cowles “Under- and Overflow Detection in the Residue Logarithmic Number System,” IEEE Symposium on Computer Arithmetic (ARITH 26), Kyoto, 2019.
  29. Ι. Kouretas and V. Paliouras, “Hardware Implemenation of the Softmax Activation Function,” MOCAST 2019.
  30. I. Kouretas and V. Paliouras, “Long Short Term Memory for Deep Learning,” IEEE ICECS 2018, Bordeaux, France.
  31. E. Kavvousanos, V. Paliouras, and I. Kouretas, “Simplified Deep-Learning-based decoders for linear block codes,” IEEE ICECS 2018, Bordeaux, France
  32. V. Paliouras, K. Karagianni, Y. Oster, “Quantitative evaluation of certain SET mitigation techniques for  multiply-accumulate circuits and state machines,” in Proceedings of PATMOS 2018
  33. V. Paliouras, K. Karagianni, Y. Oster, “Low-Cost Soft-Error Compensation for Transposed FIR Digital Filters,” in MOCAST 2018.
  34. I. Kouretas and V. Paliouras, “Logarithmic Number System for Deep Learning,” MOCAST 2018.
  35. A. Kalampoukas and V. Paliouras, “A novel algorithm and hardware architecture for low-complexity soft demappers”, MOCAST 2018.
  36. Ch. Andriakopoulos and V. Paliouras, “Data Representation and Hardware Aspects in a Fully-Folded Successive-Cancellation Polar Decoder,” MOCAST 2018.
  37. G. Perris – Samios and V. Paliouras, “An approximate hardware check node for λ-min-based LDPC decoders,” 2017 25th European Signal Processing Conference (EUSIPCO), Kos, 2017, pp. 1354 – 1357. doi: 10.23919/EUSIPCO.2017.8081429
  38. G. Tsiaras and V. Paliouras, “Logarithmic Number System Addition-Subtraction using Fractional Normalization,” IEEE ISCAS 2017, 2017.
  39. G. Tsiaras and V. Paliouras, “Multi-operand logarithmic addition/subtraction based on Fractional Normalization”, MOCAST 2017.
  40. Alexios Thanos and Vassilis Paliouras, “Trade-offs for Massive MIMO Uplink Detection Based on Newton Iteration Method,” MOCAST 2017.
  41. N. Avouris, K, Sgarbas, V. Paliouras, M. Koukias, “Work in progress: An introduction to computing course using a Python-based experiential approach,” 2017 IEEE Global Engineering Education Conference (EDUCON), Athens, Greece, 2017, pp. 1663-1666.
  42. Ch. Archonta, Nikos Kanistras and Vassilis Paliouras, “Novel multi-Gbps bit-flipping decoders for punctured LDPC codes,” MOCAST, 2016.
  43. K. Papachatzopoulos, V. Paliouras, “Reduction of delay variations in arithmetic circuits using a redundant representation,” MOCAST, Feb 2016.
  44. K. Papachatzopoulos, I. Kouretas, V. Paliouras, “Dynamic delay variation behaviour of RNS multiply-add architectures,” ISCAS 2016.
  45. Ch. Vasilopoulos and V. Paliouras, “A Technique for the Identification of Trapping Sets in LDPC Codes,” pp. 838 – 841, IEEE ICECS 2014.
  46. P. Mermigkas and V. Paliouras, “Effective Sum of Squares Implementation for BPSK Soft-Decision Decoding,” pp. 822 – 825, IEEE ICECS 2014.
  47. N. Kanistras and V. Paliouras, “A semi-analytical bivariate Gaussian model of the approximation error impact on the Min-Sum LDPC decoding algorithm,” IEEE SiPS 2013, pp. 89 – 94.
  48. I. Kouretas and V. Paliouras, “Delay-Variation-Tolerant FIR Filter Architectures Based on the Residue Number System”, ΙΕΕΕ ISCAS 2013, pp. 2223 – 2226.
  49. A. Mahdi, P. Sakellariou, N. Kanistras, I. Tsatsaragkos and V. Paliouras, “Hardware design and verification techniques for Giga-bit Forward-Error Correction systems on FPGAs,” Special Session on Computational Intensive FPGA applications, ICECS 2012.
  50. P. Sakellariou and V. Paliouras, “Low-power two’s-complement multiplication based on selective activation,” ICECS 2012.
  51. P. Sakellariou and V. Paliouras, “Low-power delay sensors on FPGAs,” PATMOS 2012.
  52. A. Mahdi and V. Paliouras, “Simplified Multi-Level Quasi-Cyclic LDPC codes for low-complexity encoders,” SiPS 2012.
  53. G. Spourlis, I. Tsatsaragkos, A. Mahdi, N. Kanistras, and V. Paliouras “Error floor compensation for LDPC codes using concatenated schemes,” SiPS 2012.
  54. N. Kanistras, I. Tsatsaragkos and V. Paliouras, “Propagation of LLR saturation and quantization error in LDPC Min-Sum iterative decoding,” SiPS 2012.
  55. P. Sakellariou, I. Tsatsaragkos, N. Kanistras, A. Mahdi and V. Paliouras, “An FPGA-based Prototyping Method for Verification, Characterization and Optimization of LDPC Error Correction Systems,” International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), SAMOS XII, 2012.
  56. I. Kouretas and V. Paliouras, “Residue Arithmetic for Designing Multiply-Add Units in the Presence of Non-Gaussian Variation”, ISCAS 2012.
  57. E. Theodorakis and V. Paliouras, “On the Impact of Encoding on the Complexity of Residue Arithmetic Circuits,” pp. 149 – 152, ICECS 2011.
  58. N. Kanistras, I. Tsatsaragkos, A. Mahdi, K. Karagianni, V. Paliouras, F. Gioulekas, E. Lalos, K. Adaos, M. Birbas, P. Karaivazoglou, M. Koziotis and M. Perakis, “Digital baseband challenges for a 60GHz gigabit link,” pp. 346 – 349, ICECS 2011.
  59. R. Makri, P. Tsenes, D. Economou, Y. Papananos, D. Dervenis, M. Birbas, J. Kikidis, V. Paliouras, G. Kalivas, A. Birbas, P. Karaivazoglou, Y. Stratakos, J. Korinthios, S. Siskos, A. Xatzopoulos, J. Komninos, S. Katsikas, K. Voudouris, A. Rigas, G. Agapiou, P. Raxis, “Next Generation Millimeter Wave Backhaul Radio: Overall system design for GbE 60GHz PtP Wireless Radio of high CMOS integration,” pp. 338 – 341, ICECS 2011.
  60. I. Tsatsaragkos and V. Paliouras, “A flexible layered LDPC decoder”, pp. 36 – 40, International Symposium on Wireless Communication Systems (ISWCS)  2011.
  61. A. Brokalakis and V. Paliouras, “Using the arithmetic representation properties of data to reduce the area and power consumption of FFT circuits for wireless OFDM systems”, pp. 7 – 12, IEEE SiPS 2011.
  62. A. Mahdi, N. Kanistras, and V. Paliouras, “An encoding scheme and encoder architecture for rate-compatible QC-LDPC codes,” pp. 228 – 233, IEEE SiPS 2011.
  63. Mark Arnold, John Cowles, Vassilis Paliouras and Ioannis Kouretas, “Towards a Quaternion Complex Logarithmic Number System,” 2011 IEEE 20th Symposium on Computer Arithmetic (ARITH),  pp. 33 – 42,  Tuebingen, Germany, July 25 – July 27, 2011.
  64. Mark Arnold, Ioannis Kouretas and Vassilis Paliouras, “A Residue Logarithmic Number System ALU Using Interpolation and Cotransformation”, pp. 255 – 258, 2011 IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP), ASAP 11.
  65. I. Tsatsaragkos, N. Kanistras and V. Paliouras, “A Syndrome-Based LDPC Decoder With Very Low Error Floor”, pp. 1 – 6, 17th International Conference on Digital Signal Processing (DSP) 2011.
  66. I. Tsatsaragkos, N. Kanistras and V. Paliouras, “Multiple LDPC Decoder οf Very Low Bit-Error Rate”, 17th International Conference on Digital Signal Processing (DSP) 2011.
  67. I. Paraskevakos and V. Paliouras, “A flexible high-throughput hardware architecture for a Gaussian noise generator”, IEEE ICASSP, pp. 1673-1676, 2011.
  68. Ι. Kouretas and V. Paliouras, “RNS multi-voltage low-power multiply-add unit”, ICECS 2010.
  69. A. Spanos and V. Paliouras, “VLSI Implementation and Performance of Turbo Decoding Stopping Criteria”, ICECS 2010.
  70. Ι. Kouretas and V. Paliouras, “Multi-voltage low-power multiply-add units based on residue arithmetic,” PATMOS 2010.
  71. Ν. Kanistras, Ι. Tsatsaragkos, Ι. Paraskevakos, A. Mahdi and V. Paliouras, “Impact of LLR saturation and quantization on LDPC min-sum decoders”, in Proc. of 2010 IEEE Workshop on Signal Processing Systems (SIPS), pp. 410‑415, 6‑8 Oct. 2010.
  72. Ι. Κouretas and V. Paliouras, “Mixed radix-two and high-radix arithmetic bases for variation-tolerant design”, European Workshop on CMOS Variability (VARI) 2010.
  73. Ι. Κouretas and V. Paliouras, “Residue Arithmetic Bases for Reducing Delay Variation”, IEEE International Symposium on Circuits and Systems (ISCAS) 2010.
  74. I. Kouretas and V. Paliouras, “Residue arithmetic for variation-tolerant design of multiply-add units,” στo Proceedings of PATMOS 2009, Springer.
  75. I. Kouretas and V. Paliouras, “Variation-tolerant design using residue number system,” στο Proceedings of
    12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, 2009, DSD ’09,     2009.
  76. I. Kouretas and V. Paliouras, “High-radix residue arithmetic bases for low-power DSP systems,” 16th International Conference on Digital Signal Processing, 2009,  pp.1-6, 5-7 July 2009
  77. N. Kanistras and V. Paliouras, “Impact of Roundoff error on the decisions of the Log Sum-Product algorithm for LDPC decoding,” στο Proceedings of IEEE SiPS 2008, σελ. 100 – 105, IEEE, 2008.
  78. I. Kouretas and V. Paliouras, “Mixed radix-2 and high-radix RNS bases for low-power multiplication”, στο Proceedings of PATMOS 2008, Springer.
  79. P. Karaivazoglou, K. Karagianni, V. Paliouras, και K. Berberidis,  “Roundoff Error Effects on a Quasi-Newton Frequency Domain Channel Equalizer,” στο Proceedings of  3rd ISWPC, σελ. 638 – 641, 2008.
  80. G. Aggouras και V. Paliouras, “On the implementation of bus-based architectures for LDPC decoding,” στο Proceedings of 3rd ISWPC 2008, σελ. 642 – 645, 2008.
  81. N. Kanistras και V. Paliouras, “Impact of Roundoff Errors in LDPC Decoding,” στο Proceedings of 3rd ISWPC, σελ. 646 – 650, 2008.
  82. E. Fotopoulou, V. Paliouras and Th. Stouraitis, “A Frequency-Domain Interpolation Implementation for OFDM Transmitters,” στο Proceedings of 3rd ISWPC 2008, σελ. 628 – 632, 2008.
  83. Th. Giannopoulos και V. Paliouras, “Relationship among BER, power consumption and PAPR,” στο Proceedings of 3rd ISWPC 2008, σελ. 633 ‑ 637, 2008.
  84. D. Pettas και V. Paliouras, “Packet Detector for Multiband UWB,” στο Proceedings
    of     3rd ISWPC 2008, σελ. 781 – 784, 2008.
  85. I. Kouretas, Ch. Basetas και V. Paliouras, “Low-power Logarithmic Number System Addition/Subtraction and its Impact on Digital Filters,” στο Proceedings of IEEE ISCAS 2008, σελ. 692 – 695, Seattle.
  86. P. Karaivazoglou, V. Paliouras, K. Karagianni και K. Berberidis, “Finite Word Length Analysis of the EBA-DFE,” στο Proceedings of 3rd International Symposium on Communications, Control and Signal Processing (ISCCSP 2008), σελ. 1067 – 1071, Malta, 2008.
  87. D. Gkrimpas and V. Paliouras, “On the complexity of joint demodulation and decoding”, ΙΕΕΕ Workshop on Signal Processing System Implementation (SiPS) 2007, σελ. 669 – 674, Shanghai, 2007.
  88. Ch. Basetas, I. Kouretas, and V. Paliouras, “Low-power digital filtering based on the logarithmic number system”, PATMOS 2007, LNCS 4644, Springer, σελ. 546 – 555, 2007.
  89. S. Gidaros και V. Paliouras, “Simplified criteria for early iterative decoding termination,” στο Proceedings of ΙΕΕΕ Workshop on Signal Processing System Implementation (SiPS) 2006.
  90. Th. Giannopoulos και V. Paliouras, “Low-Complexity PTS Decoder for OFDM signals without Transmission of Side Information,” στο Proceedings of ΙΕΕΕ Workshop on Signal Processing System Implementation (SiPS) 2006.
  91. K. Karagianni, V. Paliouras, and Th. Giannopoulos, “Low-power saturated arithmetic and its application in VLSI architectures for OFDM modems,” in Proceedings of ΙΕΕΕ Workshop on Signal Processing System Implementation (SiPS) 2006.
  92. Th. Giannopoulos και V. Paliouras, “Low-power Maximum Magnitude Computation for PAPR Reduction in OFDM Transmitters”, PATMOS 2006, LNCS 4148, Springer, σελ. 203 – 213, 2006.
  93. Th. Giannopoulos και V. Paliouras, “Novel Efficient Weighting Factors for PTS-based PAPR Reduction in Low-Power OFDM Transmitters”, δεκτό  για παρουσίαση στο EUSIPCO 2006.
  94. Th. Giannopoulos και V. Paliouras, “A Novel Technique for Low-Power D/A Conversion Based on PAPR Reduction”, στο Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS’06), σελ. 4999–5002, 2006.
  95. G. Glikiotis και V. Paliouras, “A low-power termination criterion for iterative LDPC code decoders”, στο Proceedings of IEEE Workshop on Signal Processing Systems (SiPS 2005), σελ. 122–127, 2005.
  96. Κ. Karagianni και V. Paliouras, “Low-power aspects of nonlinear signal processing”, στο Proceedings of Power and Timing Modeling, Optimization and Simulation (PATMOS 2005), σελ. 518 – 527, Springer-Verlag, 2005.
  97. Th. Giannopoulos και V. Paliouras, “Low-power VLSI Architectures for OFDM Transmitters based on PAPR Reduction”, στο Proceedings of Power and Timing Modeling, Optimization and Simulation (PATMOS 2005), σελ. 177 – 186, Springer-Verlag, 2005.
  98. P. Vouzis, M. G. Arnold, και V. Paliouras, “Using CLNS for FFTs in OFDM Demodulation of UWB Receivers”, στο Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS’05), IEEE ISCAS, 2005.
  99. E. Fotopoulou and V. Paliouras, “An Efficient Computational Method and a VLSI Architecture for Digital Filtering of CP-OFDM Signals,” IEEE GLOBECOM 2004.
  100. P. Vouzis and V. Paliouras, “Optimal Logarithmic Representation in terms of SNR Behavior”, στο Proceedings of Power and Timing Modeling, Optimization and Simulation (PATMOS 2004), σελ. 760 – 769, Springer-Verlag, 2004.
  101. S. Krommydas και V. Paliouras, “Coefficient Compression for 8k FFT and the corresponding error model”, στο Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS’04), σελ. IV-89 – IV-92, Vancouver, BC, 2004.
  102. Th. Giannopoulos και V. Paliouras, “An Efficient Architecture for Peak-to-Average Power Ratio Reduction in OFDM Systems in the Presence of Pulse Shaping Filtering”, στο Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS’04), σελ. IV-85 – IV-88, Vancouver, BC, 2004.
  103. Κ. Karagianni και V. Paliouras, “Efficient Third-Order Volterra Filter Computation in the Time Domain”, στο Proceedings of 37th Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, 9 – 12 Νοεμβρίου 2003.
  104. E. Fotopoulou, V. Paliouras και T. Stouraitis, “A computational technique and a VLSI architecture for digital pulse shaping in OFDM modems”, Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS’03), σελ. ΙΙ-125 – ΙΙ-128, 2003.
  105. I. Kouretas και V. Paliouras, “High-radix redundant circuits for RNS modulo ”, Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS’03), σελ. V-229 – V-232, 2003.
  106. V. Paliouras και A. Skavantzos, “Novel forward and inverse PRNS converters of reduced computational complexity”, στο Proceedings of 36th Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, 2002.
  107. G. Dimitrakopoulos και V. Paliouras, “Graph-based optimization for a CSD-enhanced RNS multiplier”, στο Proceedings of 45th IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2002, Τομ. 3, σελ. ΙΙΙ-648 – ΙΙΙ-651, Tulsa, Oklahoma, 4-7 Αυγούστου, 2002.
  108. Ι. Kouretas και V. Paliouras, “High-radix modulomultipliers and adders”, στο 2002 International Conference on Electronics, Circuits and Systems, Dubrovnik, Croatia, Σεπτέμβριος 2002.
  109. V. Paliouras, A. Skavantzos, και T. Stouraitis, “Multi-voltage Low-Power Convolvers using the Polynomial Residue Number System”, στο Proceedings of ACM 2002 Great Lakes Symposium on VLSI (GLSVLSI), σελ. 7–11, New York, ΝΥ, Απρίλιος 2002.
  110. V. Paliouras, “Optimization of LNS Operations for Embedded Signal Processing Applications”, στο Proceedings of IEEE International Symposium on Circuits and Systems, (ISCAS’2002), σελ. ΙΙ-744–ΙΙ-747, Phoenix, AZ, Μάιος 2002.
  111. V. Paliouras, A. Skavantzos, και T. Stouraitis, “Low-Power Convolvers using the Polynomial Residue Number System”, στο Proceedings of IEEE International Symposium on Circuits and Systems, (ISCAS’2002), σελ. ΙΙ-748–ΙΙ-751, Phoenix, AZ, Μάιος 2002.
  112. V. Paliouras, J. Dagres, P. Tsakalides και Τ. Stouraitis, “VLSI Architectures for Blind Equalization Based on Fractional-order Statistics”, στο Proceedings of IEEE International Conference on Electronics, Circuits and Systems, Τομ. 2, σελ. 799 – 802, Μάλτα, Σεπτέμβριος 2001.
  113. V. Paliouras και T. Stouraitis, “Low-power Properties of the Logarithmic Number System”, στο Proceedings of 15th Symposium on Computer Arithmetic, σελ. 229–236, Vail, CO, Ιούνιος 2001.
  114. V. Paliouras και T. Stouraitis, “Signal Activity and Power Consumption Reduction Using the Logarithmic Number System”, στο Proceedings of 2001 ΙΕΕΕ International Symposium on Circuits and Systems, τομ ΙΙ., σελ. 653–656, Μάιος 2001.
  115. V. Paliouras και T. Stouraitis, “High-Radix Residue Number System Forward and Inverse Converters”, στο Proceedings of 2000 IEEE International Conference on Electronics, Circuits, and System, σελ. 858–861, Βυρητός, Δεκέμβριος 2000.
  116. V. Paliouras, Κ. Κaragianni και Τ. Stouraitis, “A Low-Complexity RNS Multiplier”, στο Proceedings of 2000 IEEE Workshop on Signal Processing Systems (SiPS 2000), σελ. 487–496, IEEE Press, 2000
  117. V. Paliouras και T. Stouraitis, “Logarithmic Number System for Low-Power Arithmetic”, στο Proceedings of International Workshop – Power and Timing Modeling, Optimization and Simulation, (PATMOS 2000), LNCS 1918, σελ. 285–294, Springer-Verlag, 2000.
  118. V. Paliouras και T. Stouraitis, “Novel high-radix Residue Number System multipliers and adders”, στο Proceedings of IEEE International Symposium on Circuits and Systems, (ISCAS’99), Τομ. I, σελ. I.451–I.454, 1999.
  119. V. Paliouras, K. E. Karagianni και T. Stouraitis, “A VLSI architecture for fast and accurate floating-point sine/cosine evaluation”, στο Proceedings of International Conference on Electronics, Circuits, and Systems, (ICECS’98), σελ. 473–476, Λισσαβώνα, 1998.
  120. V. Paliouras, J. Karagiannis, G. Aggouras και T. Stouraitis, “A Very-Long Instruction Word digital signal processor based on Logarithmic Number System”, στο Proceedings of International Conference on Electronics, Circuits, and Systems, (ICECS’98), σελ. 59–62, Λισσαβώνα, 1998.
  121. K. E. Karagianni, G. Diamantakos, V. Paliouras και T. Stouraitis, “An operation-saving geometry engine VLSI core”, στο Proceedings of IEEE International Conference on Acoustics, Speech, and Signal Processing, (ICASSP’97), Τομ. I, σελ. 607–610, Μόναχο, 1997.
  122. V. Paliouras και T. Stouraitis, “Area-time performance of VLSI FIR filters based on Residue Arithmetic”, στο Proceedings of the 23rd Euromicro Conference, σελ. 576–583, Βουδαπέστη, 1997.
  123. Ε. N. Malamas, V. Paliouras και T. Stouraitis, “Efficient algorithms and VLSI architectures for trigonometric functions in the logarithmic number system based on the subtraction function”, στο Proceedings of the Third International Conference on Electronics, Circuits, and Systems, (ICECS’96), Τομ. 2, σελ. 964–967, Ρόδος, 1996.
  124. V. Paliouras και T. Stouraitis, “A novel algorithm for accurate Logarithmic Number System subtraction”, στο Proceedings of IEEE International Symposium on Circuits and Systems, (ISCAS’96), Τομ. 4, σελ. 268–271, Ατλάντα, 1996.
  125. V. Paliouras και T. Stouraitis, “Architectural optimization for a VLSI digital hearing-aid processor”, στο Proceedings of COMBIO’96, Summer Workshop on Computational Modelling, Imaging and Visualization in Biosciences, σελ. 99–103, Σόρπον, Ουγγαρία, Αύγουστος 1996.
  126. V. Paliouras, D. Soudris και T. Stouraitis, “Designing efficient redundant arithmetic processors for DSP applications”, στο Proceedings of 38th Midwest Symposium on Circuits and Systems, (MWSCAS’95), Τομ. 2, σελ. 1272–1275, Ρίο ντε Τζανέιρο, 1995.
  127. Ι. Orginos, V. Paliouras και T. Stouraitis, “A novel algorithm for multi-operand Logarithmic Number System addition and subtraction using polynomial approximation”, στο Proceedings of IEEE International Symposium on Circuits and Systems, (ISCAS’95), Τομ. 3, σελ. 1992–1995, Seattle, 1995.
  128. Α. Rjoub, V. Paliouras και T. Stouraitis, “A full-custom implementation of an RNS multiplier”, in Proceedings of International Conference on Electronics, Circuits, and Systems, (ICECS’95), σελ. 25–28, Aμμάν, 1995.
  129. V. Paliouras, E. Kyriakis-Bitzaros, T. Stouraitis και C. E. Goutis, “Modelling of algorithms and processor arrays based on cellular automata”, στο Proceedings of 7th International Conference on Modelling Techniques and Tools for Computer Performance Evaluation, σελ. 63–66, Βιέννη, 1994.
  130. V. Paliouras, I. Orginos και T. Stouraitis, “Multi-operand Logarithmic Number System adders and subtractors based on polynomial approximation”, στο Proceedings of International Conference on Electronics, Circuits, and Systems, (ICECS’94), Κάιρο, 1994.
  131. V. Paliouras και T. Stouraitis, “Systematic design of multi-modulus/multi-function Residue Number System processors”, στο Proceedings of IEEE International Symposium on Circuits and Systems, (ISCAS’94), Τομ. 4, σελ. 79–82, Λονδίνο, 1994.
  132. V. Paliouras, D. Soudris και T. Stouraitis, “Methodology for the design of signed-digit DSP processors”, στο Proceedings of IEEE International Symposium on Circuits and Systems, (ISCAS’93), σελ. 1833–1836, Σικάγο, 1993.
  133. D. J. Soudris, V. Paliouras, T. Stouraitis, A. Skavantzos and C. E. Goutis, “Systematic design of full adder-based architectures for convolution”, στο Proceedings of IEEE International Conference on Acoustics, Speech, and Signal Processing, (ICASSP’93), Τομ. Ι, σελ. Ι-389–Ι-392, 1993.
  134. D. J. Soudris, V. Paliouras και T. Stouraitis, “Systematic development of architectures for multidimensional DSP using the Residue Number System”, στο Proceedings of IEEE International Conference on Acoustics, Speech, and Signal Processing, (ICASSP’92), Toμ. III, σελ. ΙΙΙ-397–ΙΙΙ-400, 1992.
  135. V. Paliouras, D. J. Soudris και T. Stouraitis, “Systematic derivation of the processing element of a systolic array based on Residue Number System”, στο Proceedings of IEEE International Symposium on Circuits and Systems, (ISCAS’92), σελ. 815 – 818, 1992.