The VLSI Design Laboratory, University of Patras, founded in 1986, have long and extensive experience in basic and applied research projects. Research activities cover all aspects of VLSI hardware and system design and optimization. Novelties and breakthroughs are sought both in integrated system design methodologies as well as targeted application domains of high industrial relevance. Current research activities include VLSI systems for telecommunication applications and signal processing, forward error correction, security and cryptography, VLSI systems for video applications, reconfigurable systems and FPGAs, lowpower design, highperformance parallel systems, processvariationtolerant design techniques and architectures, applicationspecific processor design and optimization, hardwaresoftware codesign and partitioning.

The VLSILAB is staffed by four faculty members, six post doctoral researchers, and 12 PhD students. Furthermore a large number of graduate and undergraduate students are involved in research activities in the context of their diploma and MsClevel theses.

The team is wellequipped with dedicated computational facilities, laboratory equipment and hardware prototyping systems and tools, and complete EDA software design flows, which enable carrying out several largescale research projects. In addition toits dedicated infrastructure, detailed below, the lab has continuous access to campuswide and departmental facilities.

The group has extensive experience in the development of baseband hardware systems for telecommunication applications. In the proposedproject the VLSI Design Lab will work on research and development of FEC systems. During the last three years, the group involved in this proposal has successfully completed three research projects, directly related to FEC systems implemented on hardware.


  • Under an industrial contract “VLSIFEC”, VLSILAB developed a prototype of a novel FEC system implementing iterative decoding of LDPC using various FPGA development boards, including a Virtex5 VLX330.
  • In the context of the “nexgen miliwave” project, cofinanced by Hellenic Funds and by the European Regional Development Fund (ERDF) under the Hellenic National Strategic Reference Framework (NSRF) 20072013, within the Programme “Hellenic Technology Clusters in Microelectronics Phase2 Aid Measure,” the group developed a gigabitrate LDPCbased FEC system for a 60GHz pointtopoint wireless link. Activities carried out by the VLSILAB were the definition of the LDPC codes to be used, hardware implementation of scalable iterative decoders, design of gigabitrate decoders, functional verification of the baseband chain, using Virtex7 technology.
  • Under the contract “Fast Flexible FEC”, funded by Antcor S.A, hardware prototypes of several FEC blocks, implementing decoding of convolutional codes and LDPC codes compliant with the IEEE 802.11ac standard, have been successfully designed, implemented, and verified, onto Virtex5 technology, while novel solutions achieved led to three US patent applications.

Ongoing funded directlyrelated research activities include the development of a FEC system for a wireless gigabitrate pointtopoint connection operating in the E Band.

The group has dedicated computing infrastructure: A large number of highperformance PC workstations running windows and linux, prominent among them is a Dell PowerEdge900 server: a sixteencore machine with 64GB RAM, running 64bit Red Hat Enterprise Linux (RHEL). The group is equipped with necessary tools for testing and digital design debugging: Tektronix TLA7000 Logic analyzer, 68 channels, 8 GHz MagniVu Timing, 450 MHz State Clock equipped with FS2 FPGAVIEW, TLA support for XILINX FPGAS. Also, there is a PGA3 300MHz pattern generator. Prototyping equipment: A variety of development boards and kits based on Spartan 3E, Virtex4, 5, 6, 7, and Kintex7devices. The particular boards target embedded systems, DSP, and ASIC prototyping.EDA software: Complete set of tools available via Europractice to support all aspects of electronic design, including HDL model development, synthesis, simulation and verification, timing analysis, power analysis, place, and route. Full Mentor Graphics suite: Complete set of tools for all design procedures ranging from systemlevel HDL specification to backend IC development support. Full Cadence IC design flow, including HDLbased frontend tools to IC backend tools. Synopsys frontend for HDL modeling, synthesis, timing, and power analysis and optimization tools and backend support.Xilinx tools for FPGA prototyping of embedded systems and ASICs: Vivado, EDK, ISE Foundation, XST synthesis, IMPACT for binary file generation, ILA (Integrated and Logic Analyzer), and Chipscope Pro for FPGA debugging. Modelbased system design flows based on Matlab, Simulink from Mathworks, and SystemGenerator from Xilinx.Software tools for architecture exploration and compiler optimizations.