Ioannis Kouretas


Dr. Ioannis Kouretas received the diploma degree in computer engineering and informatics, in 2001 from the Computer Engineering and Informatics Department, University of Patras, Greece. In 2003 he earned his M.Sc. degree in Hardware and Software Integrated Circuits from the Computer Engineering and Informatics Department, University of Patras, Greece. From 2003 he worked a research fellow at the VLSI Laboratory of the Electrical and Computer Engineering Department, University of Patras. In 2012 he received his Ph.D. from the Electrical and Computer Engineering Department, University of Patras, entitled “Low-power and low-variation RNS Circuits”, where he is currently working as faculty lecturer teaching digital system design courses. From  Jul 2021 to Jan 2022, he worked on the research project “Sampling technique definition using coding, and FPGA firmware and electronic circuits development for a Mezzanine electronic card tester.” Since October 2021 he has been working on the research project “Alternative Numbering Systems and Architectures for AI on Edge Devices” in collaboration with Khalifa University, Abu Dhabi(United Arab Emirates)  – College of Engineering. Towards this purpose, he has visited Khalifa university from March 2022 to May 2022 as a Visitor Researcher. He is a member of the team of inventors of the patent “Hardware activation function calculation in artificial neural Residue Number System (RNS) networks”. His research interests include computer arithmetic, low-power digital design, hardware design for deep learning, and VLSI signal processing architectures. Some recent publications are in the field of Neural Network Hardware Implementation such as (I. Kouretas and V. Paliouras, “Hardware Implementation of a Softmax-Like Function for Deep Learning,” Technologies, vol. 8, no. 3, p. 46, Aug. 2020.,), (“I. Kouretas and V. Paliouras, “Simplified Hardware Implementation of Memoryless Dot Product for Neural Network Inference,” 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021, pp. 1-5,., Daegu, Korea”) and (“I. Kouretas and V. Paliouras, “Hardware Aspects of Parallel Neural Network Implementation,” 2021 10th International Conference on Modern Circuits and Systems Technologies (MOCAST), Thessaloniki, Greece”).

google scolar


ORCID 


Ioannis Kouretas
Laboratory Staff
University of Patras
Electrical and Computer Engineering Department
VLSI Design lab
Patras Rio, T.K. 26500
Tel.  2610997220
Email. kouretas@ece.upatras.gr
Web. http://www.ics.ece.upatras.gr/people/ioannis-kouretas/