Contact Vassilis Paliouras for 2023 diploma theses projects in the following areas (yet, not limited to):
- Hardware architectures for machine learning
Focus is on the optimization of model parameter representation targeting
minimization of storage and hardware complexity requirements.
FPGA implementation. - Approximate computing architectures
Evaluation of trade-offs exploiting approximate hardware arithmetic operations
taking into account the impact on common digital filtering and machine learning applications,
with a focus on reccurent structures. FPGA implementation. - Hardware architectures for Polar decoders in 5G
Polar codes are capacity-achieving codes adopted in current 5G standards.
Hardware, performance and power trade-offs will be quantitatively evaluated
targeting the specifications defined by the relevant 5G standard.
FPGA implementation. - Hardware architectures for LDPC decoders in 5G
The focus is on hardware for iterative decoders under the specifications
set by 5G NR. FPGA implementation. - Nonbinary LDPC decoder architectures
Hardware architectures for nonbinary LDPC decoding will
evaluated for the 5G NR specifications. FPGA implementation. - Hardware for homomorphic encryption
Homomorphic schemes provide basic arithmetic operations on encrypted data without
requiring plaintext. Impact on basic machine-learning and signal processing
applications will be evaluated. FPGA implementation.