VLSI LAB
Skip to content
  • Home
  • News
  • Infrastructure
  • People
    • Odysseas Koufopavlou
      • Projects
      • Publications
      • Publications (dblp)
    • Vassilis Paliouras
      • R&D Projects
      • Publications
      • Publications @ dblp
      • Technical activities
      • PhD Students
      • MSC students
      • Graduates
    • George Theodoridis
      • Projects
      • Publications
    • Ioannis Kouretas
      • Publications
      • Publications (dblp)
  • Activity
    • Architectures and Hardware Structures
    • Chip Design
  • Research Areas
    • RLNS
  • ΔΠΜΣ – ΟΣΥΛ

PhD thesis defense: “VLSI architectures for error correction in digital communication systems”

By Vassilis Paliouras | 14 December 2018
0 Comment

Wednesday 19 December 2018, 18:00, General Assembly room: Ioannis Tsatsaragkos will present his PhD thesis on “VLSI architectures for error correction in digital communication systems.”

Category: academic news thesis Vassilis Paliouras

About Vassilis Paliouras

Professor google scholar

View all posts by Vassilis Paliouras →
Post navigation
← Thesis defense: “Data representation and adder architectures in the presence of variations” Talk with industry: MEAZON →

Projects

Καινοτόμος Ψηφιακός Πομπός Ολοκληρωμένων Συστημάτων - HIDIT

News

  • Diploma theses – 2023
  • New publication on RNS CNN hardware accelerators
  • New publication on stochastic arithmetic
  • HSIS MSc Thesis Defence – Dimitris Kompostiotis
  • Diploma thesis defence – Dimitris Anyfandis
  • Diploma thesis defence – Stavros Tsikrikas

Calendar

December 2018
M T W T F S S
 12
3456789
10111213141516
17181920212223
24252627282930
31  
« Oct   Jan »

Tags

HSIS (1) OSYL (1) Presentation (1) Thesis Defense (1) Μεταπτυχιακό (1) ΟΣΥΛ (2)
VLSI LAB @ Electrical and Computer Engineering - University of Patras
Iconic One Theme | Powered by Wordpress
Font Resize
Accessibility by WAH